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2010 Conference Information Coming Soon
Ken Hansen, Abstract: As economies the world over seek to overcome the recent downturn, the primary engine that will drive growth will be technological innovations. Three fundamental market forces are shaping the market today and foreseeably into the future: Health and Safety, Going Green, and the Net Effect. These market trends and their derivatives will provide new growth opportunities for semiconductors and will also require innovation to provide value along different dimensions. This keynote will address the innovation pipeline in embedded electronics and present a vision for growth driven by semiconductors. Biography: Ken Hansen's work is focused at improving design efficiency and reducing product cost across all the Freescale businesses. Previously, he has held various senior positions at Freescale and Motorola leading Research and Development teams. Hansen received his BSEE and MSEE (1976) from the University of Illinois, is a Senior Member of the IEEE, and holds 12 U.S. patents. Ken is an industry veteran having 33 years of analog and digital design experience in bipolar, CMOS, and BiCMOS technologies primarily in the area of wireless communications.
Krisztián Flautner Abstract: Flautner received a PhD in computer science and engineering from the University of Michigan, where he is currently appointed as a visiting scholar. He is a member of the ACM and the IEEE. 
Abstract: The continuing demand to integrate more transistors on 2D chips, the slowing of the pace of CMOS feature size scaling, and the increasing interconnect delay issues are significant challenges to traditional VLSI technology. Recent development in 3D integrated VLSI technology;provide attractive technology capabilities for current and future technology nodes that address these challenges. This tutorial will examine key technologies being developed in industry and in academia that are enabling 3D-VLSI, will explore some of the new challenges and implications they present to current 2D design methodologies, and will present some of the design and system considerations in applying 3D VLSI. Biography: Mr. Carpenter joined IBM in 1983 and has been a Research Staff Member at IBM Research, Austin since 1998. His research activities have included energy efficient dynamically-scalable embedded processors, high-performance circuits, and novel SMP system architectures. His current research includes 3D VLSI design and integration, efficient energy converters, and post-CMOS devices. He is the technical lead on the IBM 3DI design evaluation effort and is the IBM industrial consultant to the South West Academy of Nanotechnology (SWAN) at UT Austin.
Harish Krishnaswamy Abstract: Multiple-antenna transceivers will play a crucial role in emerging silicon-based millimeter-wave wireless applications, both for communication and wireless sensing. The first segment of this talk will cover new architectures and circuit concepts that exploit silicon integration for the implementation of high-performance multiple-antenna transceivers at low area and power consumptions. A new nonlinear multi-functional phased-array architecture utilizes the nonlinear injection-pulling properties of a tuned ring oscillator locked in a PLL to achieve phased-array functionality at a fraction of the area and power requirements of conventional techniques. A new MIMO-radar architecture, termed the RF-Multibeam Spatio-Temporal RAKE architecture, combines waveform diversity with multi-beam beamforming to isolate line-of-sight (LoS) reflections from multipath for enhanced radar scene reconstruction. Experimental results from several CMOS mm-Wave prototypes will be presented. The second segment of this talk focuses on the implementation of power-efficient high-data-rate baseband processors for mm-Wave transceivers. The partitioning of baseband signal processing between the analog and digital domains is analyzed within the context of technology scaling. It is found that application-specific analog pre-processing techniques reduce the requirements on the analog-to-digital converter (ADC) and lead to power-efficient implementations. Biography: Harish Krishnaswamy received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology-Madras, India, in 2001, and the M.S. and Ph.D. degrees in Electrical Engineering from the University of Southern California (USC) in 2003 and 2009, respectively. He joined the EE department of Columbia University as an Assistant Professor in January 2009. In the summers of 2006 and 2007, he held internship positions at Sierra Monolithics, Inc. and the IBM T. J. Watson Research Center respectively, and worked on mm-wave building blocks for wireless transceivers. He received the IEEE International Solid State Circuits Conference (ISSCC) Lewis Winner Award for Outstanding Paper in 2007. He also received the Best Thesis Award from the USC Viterbi School of Engineering in 2009.
Andreas Gerstlauer Abstract: The continuous increase in size, complexity, and heterogeneity of embedded system design has introduced new challenges in their modeling and implementation. Multi-Processor System-on-Chip (MPSoC) design requires high speed models for early verification and performance evaluation. As a result, electronic system level (ESL) modeling has moved up in abstraction from cycle accurate RTL to timed and untimed transaction-level models (TLMs). However, the open question is how to get from a high level system description to a hardware/software implementation? The goal of this tutorial is to answer such questions and to provide system designers and managers with new insight into ESL modeling concepts and synthesis techniques for MPSoCs. In this tutorial, we will cover the key concepts and state of the art tools for MPSoC design. We will discuss TLM semantics for automatic model generation, methods for automatic design space exploration, and hardware/software synthesis. This tutorial is targeted towards embedded software and hardware developers, engineers who use or are interested in using ESL design tools, managers of system designers, and verification engineers. Biography: Andreas Gerstlauer received a Dipl.-Ing. degree in Eletrical Engineering from the University of Stuttgart , Germany in 1997 and M.S. and Ph.D. degrees in Information and Computer Science from the University of California, Irvine (UCI) in 1998 and 2004, respectively. Prior to joining UT Austin in 2008, he was an Assistant Researcher in the Center for Embedded Computer Systems (CECS) at UC Irvine, leading a research group to develop electronic system-level (ESL) design tools. Commercial derivatives of such tools are in use at the Japanese Aerospace Exploration Agency (JAXA) and NEC Toshiba Space Systems among others. Dr. Gerstlauer is co-author on 3 books and more than 30 conference and journal publications, and his paper on OS modeling was reprinted as one of the most influential contributions at DATE. He has presented in numerous conference and industrial tutorials, and serves on the program committee of major conferences such as DATE and CODES+ISSS. Dr. Gerstlauer's research interests include system-level design automation, system modeling, design languages and methodologies, and embedded hardware and software synthesis.
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