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Jacob Abraham holds the Cockrell Family Regents Chair in Engineering at The University of Texas at Austin. He is also director of the Computer Engineering Research Center. He received the bachelor's degree in electrical engineering from the University of Kerala, India, in 1970. His M.S. degree, in electrical engineering, and Ph.D., in electrical engineering and computer science, were received from Stanford University, Stanford, California, in 1971 and 1974, respectively. He received the 2005 IEEE Emanuel R. Piore Award and is on the ISI list of the most cited researchers in the world.

Michel Agoyan is a research engineer at the CEA-LETI. Since he joined the CEA-LETI in 2006 he worked in the Smart Card industry. His research focuses on secure hardware architecture including the design methodology. He is graduated in Electronic Engineering from the Institue National des Sciences Appliquées de lyon.

Melinda Agyekum is a Ph.D. student in the Department of Computer Science at Columbia University. She received her BS degree in Computer Engineering from the Georgia Institute of Technology and her MS degree in Computer Science from Columbia University. She has been employed as an intern with several companies including Intel and Goldman Sachs. In 2008, Melinda received an Intel PhD Fellowship for her work in asynchronous digital systems. The goal of Melinda's research is to provide low-power encoding techniques that will allow asynchronous communication to become more tolerant of dynamic variability.

Mustafa Aktan received the B.S., MS, and PhD degrees in Electrical Engineering from Bogazici University, Turkey in 1999, 2001, and 2007 respectively. He is currently a Postdoc at University of Texas at Dallas. His research interest is in the low-power design of digital circuits.



Charles J. Alpert received two undergraduate degrees from Stanford University in 1991 and his Ph.D. from UCLA in 1996 in Computer Science. Chuck serves as the technical lead for the design tools group at IBM’s Austin Research Laboratory, focusing on design automation algorithms for physical synthesis and design closure. He was named an IEEE fellow in 2005. Chuck has received three Best Paper Awards from the Design Automation Conference. He has served as chair for the International Symposium on Physical Design and the Tau Workshop on Timing Issues.

Syed Askari received the B.Tech.degree in Instrumentation Engineering from Institute of Engineering & Technology, India in 2003 and M.Sc. in Electrical Engineering from Royal Institute of Technology (KTH), Sweden in 2006. He is currently a Ph.D. student at University of Texas at Dallas. His research interest includes fault tolerant Analog and Mixed signal circuit design.

Shayak Banerjee is a Ph.D. student at the University of Texas - Austin. He did his undergraduate from the Indian Institute of Technology, Kharagpur in 2001. He is also the recipient of the IBM Ph.D. Fellowship from 2008-2010. His research interests are in OPC/RET algorithms and DFM.

 

Mehmet Basoglu is a Ph.D. student in the Department of Electrical and Computer Engineering at The University of Texas at Austin. He received his B.Sc. degree in Electrical Engineering and Computer Science from The University of California at Berkeley in 2007 and his M.S. degree in Electrical and Computer Engineering from The University of Texas at Austin in 2009. He has been employed as an intern with several companies including Samsung Electronics and The University of California, Irvine - Center for Functional Onco-Imaging. Currently, for his doctoral degree, his research efforts include techniques to improve multi-core processor energy efficiency and lifetime through careful analysis of performance-degrading phenomena such as Negative Bias Temperature Instability (NBTI). Mehmet is an IEEE student member.

Paul Bassett is currently the circuit design manager for Qualcomm's DSP core design group located in Austin.  He has over 20 years experience in processor circuit design working for a wide range of companies: BBN, Kendall Square Research, Ross Technologies, Alchemy Semiconductor, AMD and Qualcomm. He has degrees from Texas A&M and MIT.

Stephen Bijansky received a BS in EE from the University of Delaware and a MS in ECE from Carnegie Mellon University. He is currently a Ph.D. student in the ECE department at UT. In the past, he had internships at Magma and Pyxis, and he is currently doing an internship at Qualcomm in the custom circuits group. His current research interests include investigating ways to reduce the effects of process variation and low power circuit design.

Kalyana C. Bollapalli is a Masters student in the Department of Electrical and Computer Engineering at Texas A&M University, College Station. He received his B. Tech degree in Electrical Engineering from Indian Institute of Technology (IIT) Bombay, India in 2004. After which he worked as an Engineer in the Automotive Microcontrollers division of Infineon Technologies till 2007. Where he worked on modeling and performance estimation. His current research interests include low power methodologies, circuit design, logic minimization and algorithms for VLSI CAD.

James F. Buller James F. Buller is Fellow and Team Leader in the Technology Foundations Department at GLOBALFOUNDRIES.  Prior to this he was an AMD Fellow and Section Manager in the Logic Technology Development organization at Advanced Micro Devices.  He received his B.A degrees in Mathematics and Physics from Albion College and Masters Degree in Engineering Physics from the University of Virginia.  His current interests include novel passives and analog device integration for CMOS microprocessors, performance-power predictions, and circuit based performance metrics.  Jim also developed many advanced CMOS transistors for high performance microprocessors, as well as non-volatile device technologies. Prior to joining GLOBALFOUNDRIES and AMD, Jim worked at Harris Semiconductor developing radiation hardened CMOS device transistor technologies for space and government applications.  Mr. Buller has more than 30 granted U.S. patents, and more than 35 publications / conference presentations.

Derek Chiou received his Ph.D., S.M. and S.B. degrees from the Electrical Engineering and Computer Science Department at the Massachusetts Institute of Technology. There he was a member of the Computation Structures Group. He was an architect of the StarT-Voyager machine as well as the StarT-NG machine. After completing his Ph.D., Dr. Chiou became a system architect at Avici Systems. Prof. Chiou is interested in computer architecture, parallel computer architecture, Internet router architecture and computer engineering.

Salim Chowdhury received his Ph.D. degree in 1986 from the University of Southern California, Los Angeles. From 1986 to 1983, he taught at University of Iowa, Iowa City where he obtained multiple research grants from National Science Foundation. He had been working with semiconductor industries since then, first with Motorola where he was involved with designing 68060 and PowerPC microprocessors. He has developed multiple CAD tools for the extraction and simulation of clock network, and timing and power optimization. Currently, he is a senior manager at SUN Microsystems Inc. at their Austin Microelectronics design center. Dr. Salim Chowdhury obtained a best paper award from DAC and holds numerous patents and publications. He is currently serving as a member of the technical program committee for ISPD 2010.

Kinchit Desai is a Ph.D. student in the Department of Electrical Engineering at University of Texas at Dallas, Richardson. He received his bachelor degree in Electronics and Communications Engineering from Gujarat University, India in 2005 and his MS degree in Electrical Engineering from University of Texas at Dallas, Richardson in 2009. Currently, for his doctoral degree, his research efforts include various aspects of VLSI and mixed signal design.

Duo Ding is currently a 2nd year PhD student at UT Austin Design Automation group. Duo got his MSE degree at UT Austin June 2008. His research interests mainly lie in (1) Novel Applications for Design for Manufacturability/Yield; (2)EDA/CAD for VLSI Physical Design Automation; (3) CAD and Mathematical Optimizations for Emerging Technologies (3D IC, Nano-technology, GPU/Network-on-Chip).

Nathalie Drach is a professor in computer science at the University of Paris 6, France. She received his Ph.D. degree in computer science from Rennes University, INRIA, in 1994, for her dissertation on pipeline and cache organizations for high-performance processors. She also was an associate professor at the University of Paris-Sud. Nathalie Drach is interested in computer architecture for high-performance embedded systems, parallelization techniques for multicore and iterative compilation techniques.

Mattan Erez is an assistant professor of Electrical and Computer Engineering at The University of Texas at Austin. He holds a B.A. in Physics (Technion, 1999) and a B.Sc. (Technion, 1999), M.S. (Stanford, 2002), and Ph.D. (Stanford, 2007) in Electrical Engineering. He has received several best paper awards at international conferences. Dr. Erez's research focus is computer architecture and programming models. Specifically, he is interested in the critical aspects of locality, parallelism and bandwidth constraints to overcome the limitations of today's architectures. One goal is to improve cooperation between the hardware, compiler and programmer in order to enable new levels of performance, efficiency and code portability.

Patrick Green received his BS in Electrical Engineering from the University of Arizona, Tucson and is currently on track to receive his MS in Electrical Engineering at the University of Arizona, Tucson in December 2009. During his MS program he has focused on mixed signal design. Mr. Green is currently employed by the Air Forces Flight Test Center where he integrates new capabilities on to state of the art aircraft.

Kanupriya Gulati is a Ph.D. student in the Department of Electrical and Computer Engineering at Texas A&M University, College Station. She received her BE degree in Computer Engineering from Delhi College of Engineering, India in 2003 and her MS degree in Computer Engineering from Texas A&M University, College Station in 2006. She has been employed as an intern with several companies including Cadence Research Laboratories, Intel, Mentor Graphics and Atrenta. Currently, for her doctoral degree, her research efforts include various aspects of VLSI design like optimizing logic synthesis and accelerating CAD algorithms in hardware. Kanupriya is an IEEE student member.

Huihua Huang is a Ph.D. student in the Department of Electrical Engineering at University of Texas at Dallas, Texas. She received her bachelor degree in Engineering from South China University of Technology, China in 2000 and her MS degree in Electrical Engineering from Southern Methodist University, Texas in 2004. Currently, for her doctoral degree, her research efforts include high speed ADCs and mixed signal design.

Naras Iyengar received his MSEE from University of Cincinnati.  He has developed various high speed and application specific SRAMs and DRAMs at Texas Instruments and SGS Thompson. He joined the PowerPC design team in 1993 as a member of IBM contributing to their memory subsystems. As Global Leader and director of Motorola/Freescale PowerPC design team, has led the development of numerous high performance PowerPC microprocessors in bulk and SOI technologies for both compute and embedded applications.  Recently he was part of a Freescale cellular design team developing highly integrated low power SOC for cellular applications. Currently he is a consultant and serves as Vice President of IP Testchip Design Services LLC.

Rouwaida Kanj received the B.Eng. (with high distinction) from the American University of Beirut, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois Urbana-Champaign in 2000 and 2004, respectively. She is currently with the Tools and Technology team at IBM Austin Research Labs. Prior to this position, she held multiple internships with the IBM EDA Group in Fishkill. She worked on modeling SOI effects, noise characterization of CMOS circuits, library characterization of novel circuit technologies, and is currently involved in variability driven SRAM analysis. Dr. Kanj was a recipient of three IBM Ph.D. Fellowships, is the author of several technical papers and two pending patents.

Sunil P Khatri received his B.Tech (EE) degree from IIT Kanpur, his M.S.(ECE) degree from the University of Texas, Austin, and the Ph.D. in EECS from the University of California, Berkeley. Sunil is currently an Assistant Professor in ECE at Texas A&M University. His research interests include novel VLSI design approaches to address issues such as power, cross-talk, and radiation tolerance, logic synthesis as well as cross-disciplinary applications of these topics. He has coauthored about 120 technical publicatons, 5 United States Patent awards, one book and a book chapter. His work has received two best paper awards, and two best paper nominations. Sunil's research is supported by Intel Corporation, Nascentric Inc,, Lawrence Livermore National Laboratories and the National Science Foundation.

Po-Yu Kuo is a Ph.D. student in the Department of Electrical Engineering at University of Texas at Dallas, Richardson. He received his bachelor degree in Electrical Engineering from Tamkang University, Taiwan in 2002 and his MS degree in Electrical Engineering from University of Texas at Dallas, Richardson in 2006. Currently, for his doctoral degree, his research efforts include various aspects of VLSI design like high level logic synthesis and CAD algorithms in hardware.

Ka Leung serves as director of engineering for Silicon Laboratories’ wireline products.  From 2005 to 2007, he was a director of engineering at Silicon Laboratories in the Microcontroller division.  Mr. Leung joined the company with the acquisition of Cygnal Integrated Products in 2003.  Previously, he served as design manager at Burr-Brown and Crystal Semiconductor.  Mr. Leung holds 43 patents in data converter and analog mixed-signal processing and has published ten journal and conference papers including two for the International Solid-State Circuit Conference.  Mr. Leung received bachelor’s degree and master’s degree in electrical engineering from the University of Arizona.

Kaijun Li is a Ph.D. student in the Department of Electrical and Computer Engineering at Boise State University. He received his B.E degree from the Harbin Institute of Technology in 2004 and his M.S. degree from Tsinghua University in 2007. His current research includes high speed ADCs using K-Delta-1-Sigma modulator.

 

Bao Liu received his Ph.D. degree in CS in University of California, San Diego in 2003, and his M.S. and B.S. degrees in EE in Fudan University, China in 1996 and 1993, respectively. Prior to joining the ECE department at UT San Antonio in 2008, he was a post-doctoral research associate at UCSD, and worked with Tabula, Cadence, Incentia, Connexant, and China IC Design Center. His research interests include VLSI design variability and reliability analysis, robust, high performance and low power design, nanoelectronic architecture, and emerging technologies. He has published over 40 journal articles and conference papers, received a Best Paper Award in International Conference on Computer Design in 2005, and a Best Research Award in UCSD Research Review 2002. He serves as co-chair of Emerging Design and Technology subcommittee in ISQED since 2006.

Kaveri Mathur works in the Technology Foundations group at GLOBALFOUNDRIES. Prior to this, she worked in the Logic and Technology Development group at AMD. She received her Master’s degree in Electrical Engineering from Texas Tech University, Lubbock. Prior to joining AMD and GLOBALFOUNDRIES, she worked as an intern in the Non-Classical CMOS group at SEMATECH. Her current interests include analog passives device suite definition, technology-design interactions, test structure design, characterization, and debug.

Michael N Michael is a component design Engineer at Intel Folsom since 2008, where he is engaged in power management pre-silicon validation of microprocessors. He received his BS degree from University of Jordan in 2006, and his MS degree from Rochester Institute of Technology in 2009, both in Computer Engineering.


Baker Mohammad is a design Engineer at Qualcomm Austin where he is engaged in designing the next generation Qualcomm DSP processor.  Prior to joining Qualcomm he worked on a wide range of processors at Intel corporation.  He has over 10 years experience in processor design with emphasis on circuit and physical design. He received the B.S degree from the University of New Mexico, Albuquerque, and the M.S. degree from Arizona State University, Tempe, both in electrical engineering.  He is pursuing his PHD in Electrical Engineering degree from the University Of Texas at Austin working with Professor Jacob Abraham and Professor Adnan Aziz.

Bassam Mohd received a BS in Computer Engineering from the KFUPM of Dhahran-KSA and a MS in Computer Engineering from University of Louisiana at Lafayette. He worked for several semiconductor companies including Intel, SUN and Synopsys. He is currently working for Qualcomm's Austin DSP group. His experience spans circuit design, verification and power analysis. He is also a part-time Ph.D. student in the ECE department at UT. His interests include DSP designs and power reduction/estimation techniques.

Dennis Montierth is a Product Engineer at Micron Technology of Boise with 9 years of experience working on DRAM and CMOS imagers. Prior to working with Micron he was employed at Autoliv where he worked on the research and development of automotive air bags. He recieved a B.S. degree in Physics from Weber State University in Ogden, UT followed by a M.S.in Electrical Engineering from Boise State Univeristy. Dennis recently started the Ph.D. program at Boise State University in Electrical Engineering. He is interested in analog and mixed signal design.

Sani R. Nassif received his PhD from Carnegie-Mellon University in the eighties. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. He joined the IBM Austin Research Laboratory in January 1996 where he is presently managing the tools and technology department, which is focused on design/technology coupling and includes activities in: model to hardware matching, simulation and modeling, physical design, statistical modeling, statistical technology characterization and similar areas.

Minh Huu Nguyen is a Ph.D student at the Systems and Secured Architecture Department of the CEA-LETI located in Gardanne, France. He received his BS in Electrical and Electronics Engineering from HoChiMinh City University of Technology, Vietnam in 2006 and his Master Science degree in Microelectronics Engineering from INSA Lyon, France in 2007. The objective of his current work consists in securing a processor-based smart card against fault attacks and side-channel attacks.

Michael Orshansky received his Ph.D. from UC Berkeley, where he was a member of the Semiconductor Device Group, in 2001. His undergraduate degree is also from UC Berkeley where he studied electrical engineering and computer science and philosophy. Prior to joining the UT faculty in 2003, he has been a Visiting Research Scientist at the Gigascale Silicon Research Center and a Lecturer at the Department of Electrical Engineering at Berkeley. Dr. Orshansky has won a NSF CAREER Award and the Best Paper Award at the 2005 Design Automation Conference.

David Z. Pan received his Ph.D. in Computer Science from UCLA in 2000. Prior to joining the UT faculty in 2003, he was a Research Staff Member at IBM T. J. Watson Research Center. His research interests include physical synthesis, design for manufacturability, and design/automation for emerging technologies. He is an Associate Editor for IEEE Transactions on Computer Aided Design and IEEE Transactions on Circuits and Systems-II, and the Program Committee Chair for International Symposium on Physical Design 2007. Dr. Pan has received many awards for his research contributions, including ACM/SIGDA Outstanding New Faculty Award, SRC Inventor Recognition Award, and IBM Faculty Award.

Dr. Tung N. Pham has 15 years of work experience in IC design. He contributed to the design of DEC Alpha processors, DEC StrongArm processors, and AMD Alchemy high performance low power MIPS and X86 processors. He is currently with Qualcomm working on the design of DSP cores for the next generation mobile phones. He has also served as an advisor and instructor for IC Design Research and Education Center and University of Technology in Vietnam. He contributed to the first RISC processor designed by Vietnam. He received his BSEE with honors from The University of Cincinnati, Ohio, MS and Ph.D. from The University of Texas at Austin.

Ravi Kiran B Ragahvendra received the B.Tech degree from National Institute of Technology Jamshedpur, India, in 2007. He is currently working toward the M.S degree in the Department of Electrical and Computer Engineering, University of Arizona, Tucson. His current research interest mainly includes Digital design and Networks on Chip.

Jaime Ramírez-Angulo is Klipsch Distinguished Professor, IEEE Fellow, and Director of the Mixed-Signal VLSI lab at the Klipsch School of Electrical and Computer Engineering, New Mexico State University in Las Cruces, New Mexico, USA. His research is related to various aspects of design and test of analog and mixed-signal Very Large Scale Integrated Circuits. He has made numerous contributions to this field which have been reported in over four hundred publications.

B. Robisson, PhD, studied electrical engineering at the Ecole Normale Supérieure de Cachan and received PhD degree in computer science from University Paris VI in 2001. Since this date, he is a researcher at the Commissariat à l'Energie Atomique (CEA). His main research topics are side channel attacks and development of cryptographic hardware. He is the author or co-author of several scientific papers. He participated in several European research projects and is now the internal coordinator for two national projects.

Siwat Saibua is currently a Ph.D. student in Electrical Engineering Department at University of Texas at Dallas. He received his B.E degree from Chulalongkorn University, Thailand in 2006 and his MSEE degree at Texas A&M University at Kingsville by the following year. During his undergraduate degree, he had an internship with National Semiconductor in Singapore as a test engineer. His current research includes inventing and developing the new algorithms to improve the performance of CAD tools.

Vishal Saxena received his Bachelors in Electrical Engineering from Indian Institute of Technology Madras, India in 2002 and his Masters from Boise State University, ID in 2007. He is pursuing his doctoral degree in ECE from Boise State University. His research interests are in high-speed data converters, delta-sigma modulators and transceiver circuit design.  

Carl Sechen received his B.E.E. from the University of Minnesota, an M.S. from M.I.T., and a Ph.D. from UC Berkeley. Starting in 1986, he was an Assistant and then Associate Professor in the Department of Electrical Engineering at Yale University. In 1992 he moved to the University of Washington, where he was a co-director of the National Science Foundation's Center for the Design of Analog and Digital Integrated Circuits (CDADIC). He is now a professor at UT-Dallas.

Mike Seningen is a Circuit Design Manager, a Principal Technologist and a Founder of Intrinsity.  Mike is a key contributor to the definition and development of Intrinsity's Fast-14TM high speed design methodology, for which he has been granted 19 patents.  Prior to Intrinsity, he designed high speed circuits and caches on numerous Sparc processors while at Ross Technology.  Mike received his BSEE from Virginia Tech in 1988 prior to joining the 68040 group at Motorola designing high speed datapath elements.  Mike is the Chair of the Solid State Circuits & Circuits and Systems Societies for the Central Texas Section of the IEEE, and is a member of the Technical Program Committee for the CICC.  Mike thrives on the challenges inherent to automating robust high speed logic and low power designs. 

Ashish Kumar Singh received the B.Tech. degree in Computer Science from the Indian Institute of Technology, Kanpur, in 2001, and Ph.D. degree in Electrical Engineering from the University of Texas, Austin, in 2007. He is currently in a postdoctoral research position with Professor Michael Orshansky. His current research is focussed on robust circuit degin in the presence of process variability. He has received the Best Paper Award at 2006 International Conference for Computer Aided Design.

Kevin G. Smith holds a B.S.E.E. from the University of Houston and a M.S.E.E. from Stanford University. He is a Senior Member of the IEEE and has worked on everything from ICs to systems. Since 2002, he has worked for Silicon Laboratories, Inc. as a Staff Applications Engineer on a variety of clock and oscillator projects. His professional interests include analog IC and board design, EMC, jitter, phase noise, and signal integrity. He may be contacted at kevin.smith@silabs.com.

Akif Sultan is a Senior Member of Technical Staff at GLOBALFOUNDRIES. He has worked at AMD for twelve years in the areas of process integration, high performance device development, device installation in Foundry, variations and device-design interactions. He led the implementation of the inclusion of layout-dependent stress effects in design within AMD. He holds 16 patents. He received his Ph.D. (1996) and MS (1993) in Electrical Engineering from UT Austin. He received his BS in Electrical Engineering from AMU, India in 1988. He taught as a Lecturer in India for three years.

Axel Thomsen attended the Polytechnical University of Braunschweig, Germany. He received his Ph. D. in Electrical Engineering in the area of analog IC design from Georgia Institute of Technology. From 1993 to 1995 he was Assistant Professor at the University of Alabama in Huntsville. From 1995 to 2001 he was a design engineer and manager at Cirrus Logic in Austin where he worked on high resolution dataacquisition ICs, ADCs, DACs and amplifiers. He is currently a principal engineer and design manager at Silicon Laboratories, where he has worked on low jitter timing circuits, PLLs, and Power ICs. Occasionally he teaches analog IC design at UT Austin. He holds 35 patents and has published 20 papers.

Janet M. Wang received the B.S. degree from Nanjing University of Science and Technology (former East China Institute of Technology), Nanjing, China, in 1991, the M.E. degree from the Chinese Academy of Sciences, Beijing, China, in 1994, and the M.S. and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, in 1997 and 2000, respectively. She was with Intel, Santa Clara, CA, and Cadence Santa Clara, from 2000 to 2002. Since 2003, she has been a Faculty Member in the Electrical Computing Engineering Department, University of Arizona, Tucson. Dr. Wang is a member of the IEEE Circuits and Systems Society and was the recipient of the 2005 National Science Foundation Career Award and 2006 Presidential Early Career Award for Scientists and Engineers.

Panduka Wijetunga is a Member of Technical Staff specializing in analog-mixed signal design at Zarlink Semiconductor. Prior to joining Zarlink Semiconductor he was a Member of Technical Staff at Rockwell Scientific, specializing in the design of large-format visible and IR imagers. He received his Ph.D. (2006), MS (1998) and BS (1996) from the University of Southern California , Los Angeles . He holds 1 patent and has published 12 papers. He is a member of IEEE.

Geng Zheng is currently working toward the Ph.D. degree in Electrical Engineering at Boise State University, Idaho. He obtained the B.S.
(2005) and M.S. (2008) degrees from Beijing Institute of Technology and Boise State University respectively specializing in Electrical Engineering. In 2005, he was with the National ASIC Design Engineering Center (Beijing, China) as an Engineering Intern. Since 2006, he has been a Student Research Assistant in Electrical and Computer Engineering Department at Boise State University. In 2008, he developed and implemented an image registration technique for a project with HP company. The technique is used for printer design verification.
Currently his research focus on high-speed analog-to-digital converter design using K-Delta-1-Sigma modulator.

Dian Zhou received the B.S degree in physics and M.S degree in electrical engineering from Fudan University, China, in 1982 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois in 1990.  He joined the University of North Carolina at Charlotte as an assistant professor in 1990, where he became an associate professor in 1995. He joined the University of Texas at Dallas as a full professor in 1999, and joined Fudan university as a Changjiang Professor in 2003 (on-leave from the University of Texas at Dallas). He serves as the Dean of Microelectronics School, and Director of National Key Lab. on ASIC at Fudan University from 2003 to 2006. His research interests include: High-speed VLSI systems, CAD tools, mixed-signal ICs, and algorithms.

Jingrong Zhou is from Globalfoundries working in Advanced Semiconductor technology development.  JR has more than 14 years of experience in semiconductor industry including manufacturing, technology development, test chip design, simulation and modeling, design rule definition and design manual publication, DRC regression and design support. During his career, JR worked  for Motorola UMC, and AMD in various key positions.  JR holds a BS in Applied Physics, a MS in EE from China.  He graduated with a PhD in EE from Arizona State University in 1991.

Jianhong Zhu is a Member of Technical Staff in the Technology Foundations Department at GLOBALFOUNDRIES. Prior to this he was a Member of Technical Staff in the Logic Technology Development at AMD. He has worked in the areas of BEOL design rule definition and validation, capacitance simulation and characterization, BEOL passives and technology-design interactions since 90 nm technology node. Prior to joining AMD, he worked in Tokyo Electron (America) on low k/Cu integration for two years. Jianhong received his Ph.D in semiconductor physics from Technical University Munich, Germany. He has more than 10 U.S. patents, and more than 25 publications/conference presentations.



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