2010 Conference Information Coming Soon


Monday, Oct 26

Title Authors
A Variation Tolerant Circuit Design Approach using Parallel Gates Sunil Khatri, Rajesh Garg
DSP Power Reduction through Generalized Carry-Save Arithmetic Chiu-Wei Pan, Yuanchen Song, Zhao Wang, Carl Sechen
Folded Strategy for SAT Solvers based on Shannon’s Theorem Siwat Saibua, Po-Yu Kuo, Dian Zhou
Low Skew Automated Clock Tree Generation Elizabeth Kiefer, William Swartz, Carl Sechen
Method of Automatic Generation and Validation of Gate Models Tung Pham, Paul Bassett
Near Optimal Power Efficiency Through Gate Sizing Mohammad Rahman, Hiran Tennakoon, Carl Sechen
Power Supply Rejection Analysis of the common 2VBE Bandgap Circuit Panduka Wijetunga
Soft Error Mitigation Techniques for Sequential and Combinational Logic Using SEUT and BISER Latches Umut Unver, Jacob Abraham, Prashant Joshi

 

 



2009 Sponsors

UT-ECE

door64

in cooperation with

IEEE Circuits & Systems

 
Full Conference Student